A differential amplifier can be employed for various purposes such as translating voltages from TTL to MOS levels or in sensing signals in a memory. It may thus be used as: (1) an address buffer in a semiconductor memory for converting transistor-transistor logic (TTL) input levels of 2.4 v ("high") and 0.8 v ("low") into MOS logic levels of 5 v ("high") and 0 v ("low"); or (2) in a sense amplifier for detecting whether a signal stored in the semiconductor memory is at a high level or a low level.
An arrangement of a conventional differential amplifier as described in (1) above is illustrated in FIG. 2.
The differential amplifier differentiates potentials between a first input signal A.sub.in (e.g. 2.4 v or 0.8 v) and a second input signal V.sub.r (e.g. 1.5 v) in response to a high level active signal .phi.1 and holds a differentially determined value in response to a high level latch signal .phi.2. The amplifier outputs complementary output signals A, A (e.g. 5 v or 0 v) and comprises P-channel field effect transistors (FETs) 1 to 4 and N-channel FETs 5 to 13. A pair of internal nodes 14, 15 are coupled to provide the output signals A and A respectively. Shown in FIG. 2 are Vcc, which is a power supply potential (first potential), and Vss, which is a ground potential (second potential).
FIG. 3 is a waveform showing an operation of the differential amplifier of FIG. 2. As shown in FIG. 3, the active signal .phi.1 and the latch signal .phi.2 are initially at low (V.sub.ss) level and nodes 14, 15 are respectively precharged to the power supply potential V.sub.cc by way of FETs 1 and 2 since these p-channel devices are on. Thus in FIG. 3, both A and A are shown initially at a high level.
When the active signal .phi.1 goes to high, this high voltage is coupled to the gate electrodes of p-channel FETs 1 and 2 to turn them off. The same high voltage of .phi.1 is applied to the gate electrodes of n-channel FETs 7 and 8 which accordingly turn on. As a result, node 15 is no longer coupled to Vcc by the source-drain path of FET 1, and is discharged by way of the source-drain paths of FETS 5, 7 and 9. Likewise, node 14 is no longer coupled to Vcc via FET 2 and is discharged by way of the source-drain paths of FETs 6, 8 and 10. Assuming that the input signal A.sub.in is 0.8 V and the input signal V.sub.r is 1.5 V, the conductance of the FET 10, having a gate electrode to which the input signal V.sub.r is applied and being an n-channel device, is greater than that of the FET 9 having a gate electrode to which the input signal A.sub.in is applied. Hence node 14 is discharged more rapidly than node 15 so that the potential of the output signal A (coupled to node 14) becomes lower than that of the output signal A (coupled to node 15), as shown in FIG. 3. The potential difference between the output signals A and A causes a conductance difference between FETs 5 and 6 since these ouput signals at nodes 14 and 15 are coupled to the gate electrodes FETs 5 and 6. If the potential of node 14 becomes lower than V.sub.cc -V.sub.tp, (where V.sub.tp is a threshold voltage of a p-channel FET), so that the gate voltage at FET 3 is more than one V.sub.tp below the source voltage, then FET 3 becomes conductive and begins to pull up its drain voltage. Since node 15 is coupled to the drain electrode of FET 3, node 15 consequently starts charging toward the power supply potential V.sub.cc so that the potential difference between nodes 14, 15 and hence the difference between output signals A and A is further increased, as depicted in FIG. 3.
When the latch signal .phi.2 coupled to the gate electrode of FET 13 goes to a high (V.sub.cc) level, FET 13 is turned on. With node 14 low, FET 11 is off, but because node 15 is high, FET 12 is on. Node 14 is coupled then to Vss via the source-drain paths of FETs 12 and 13. Thus, FET 3 turns on harder and node 15 is pulled up to V.sub.cc. After completion of such clamping, the output signals A and A are kept held at the level of ground potential V.sub.SS and power supply potential V.sub.CC irrespective of the change of the potentials of the input signals A.sub.in and V.sub.r.
The conventional differential amplifier requires two control signals, namely, the active signal .phi.1 and the latch signal .phi.2 and further requires timing controls for delaying the active signal .phi.1 and the latch signal .phi.2. The conventional amplifier is liable to cause erroneous operations when the delay time of the signals .phi.1 and .phi.2 is short since the latch signal .phi.2 rises to high at the state where the potential difference between the output signals A and A is not substantially assured. On the contrary, the conventional amplifier is liable to cause an operation speed to delay when the delay time of the signals .phi.1 and .phi.2 is long, since it takes a long time until the output signals are latched so that the output signals may be maintained long at the levels of the input signals A.sub.in and V.sub.r.
It is an object of the present invention to provide a differential amplifier capable of causing less erroneous operation.
It is another object of the present invention to provide a differential amplifier capable of operating at high speed.